Introduction
In the fast-moving field of edge AI, computation is shifting closer to the source of data to enable real-time intelligence. Demanding applications such as voice recognition and biosignal processing require ultra-low latency, high efficiency, and flexible silicon solutions beyond what off-the-shelf processors can deliver. To meet these needs, our team partnered with the client to design a custom 32 bit RISC architecture CPU core based SoC with proprietary Neural Network IP. Optimized for low power and scalability, the architecture supports diverse use cases of sensor integration and voice processing. By combining custom hardware with tailored firmware, the solution delivers seamless deployment, robust performance, and faster time-to-market. This innovation exemplifies end-to-end silicon realization, empowering next-generation edge devices with breakthrough real-time intelligence.
The Client
Requirements & Challenges
Custom Low-Power SoC
The client required a specialized SoC capable of executing proprietary neural network models.
32 bit RISC architecture based CPU-Assisted Platforms
The solution needed to run efficiently on 32 bit CPU cores for real-time applications.
Target Applications
Voice recognition and sensor signal processing demanded ultra-low latency and robust performance.
Off-the-Shelf Limitations
Existing SoCs lacked the required performance, integration flexibility, and power efficiency.
Key Initiatives & Solutions
FPGA & ASIC Expertise
32-bit RISC CPU–based ASIC Design
Developed and integrated a 32-bit RISC CPU–based ASIC, incorporating third-party IP blocks along with customer-provided IP.
RTL Design & Verification
RTL design with expertise in Verilog/SystemVerilog/VHDL, IP core development and SoC integration, Verilator-based simulation for validation, CDC handling, low-power RTL implementation using UPF/MV techniques, and configurable, reusable IP libraries.
Physical Design & Implementation
Complete physical design implmentation from netlist to GDSII with timing closure.
Boot System & Power Mode
Boot system, power mode design, and full SoC validation
FPGA Implementation
FPGA implementation and system testing
Customer IP Integration
AI-based IP Integration
Seamless integration of AI-based IPs into 32 bit MCU
Black-box Test Suites
Black-box test suites for IPs, peripherals, and ASICs
BootROM & Security
BootROM Development
BootROM and peripheral driver development
Secure Boot
Secure Boot with authenticated firmware updates
Proprietary Protocols
Proprietary host communication protocols for firmware update and debugging
ASIC Bring-Up
Automated Testing
Automated peripheral testing for ASIC and Host MCU
Driver Integration
Driver integration and customization of peripheral drivers (I2S, SPI, I2C, QSPI, MRAM, etc.)
Firmware Updates
Firmware updates and Host MCU test firmware
Testing Frameworks
Automated testing frameworks & Use case demo applications
Firmware Optimization
Code Size Reduction
Code size reduction for memory-constrained systems
Bootloader Development
Bootloader development and DMA-enabled driver modifications
Business Value
End-to-End Realization
End-to-end silicon realization from architecture to application for Edge-AI.
Production Ready SoC
Production ready SoC with robust firmware, optimized for low power operation.
Accelerated Time-to-Market
Accelerated time to market through seamless prototyping and silicon validation.
Deep Expertise
Deep Expertise in low-power Edge AI SoC development with ARM/RISC/ARC cores.
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